Semiconductor memories are used in many electronic systems to store data that may be retrieved at a later time. As the demand has increased for electronic systems to be faster, have greater data capacity, and consume less power, semiconductor memories that may be accessed faster, store more data, and use less power have been continually developed to meet the changing needs. Part of the development includes creating new specifications for controlling and accessing semiconductor memories, with the changes in the specifications from one generation to the next directed to improving performance of the memories in the electronic systems.
Semiconductor memories are generally controlled by providing the memories with command signals, address signals, clocks. The various signals may be provided by a memory controller, for example. The command signals may control the semiconductor memories to perform various memory operations, for example, a read operation to retrieve data from a memory, and a write operation to store data to the memory. The data may be provided between the controller and memories with known timing relative to receipt by the memory of an associated command. The known timing is typically defined by latency information. The latency information may be defined by numbers of clock cycles of system clocks CK and CKF.
With newly developed memories, the memories may be provided with system clocks that are used for timing the command signals and address signals, for example, and further provided with data clocks that are used for timing the read data provided by the memory and for timing the write data provided to the memory. The memories may also provide clocks to the controller for timing the provision of data provided to the controller.
The clocks provided to the memories are used to provide internal clocks that control the timing of various circuits during operation. The timing of the circuits during operation may be critical, and deviations in the timing of the clocks may cause erroneous operation. An example deviation in the timing of the clocks may be duty cycle distortion, that is, deviation from a 50% duty cycle.
Duty cycle distortion in clocks may be corrected using duty cycle correction circuits. However, conventional duty cycle correction circuits may be relatively large and require considerable area on a semiconductor die, and additionally, conventional duty cycle correction circuits consume more power than desirable. As a result, alternative circuits for reducing duty cycle distortion may be desirable.